1. Field of the invention
The present invention relates to a semiconductor integrated circuit memory, and more specifically to a semiconductor integrated circuit memory receiving at least one or more kinds of control clocks from an external source.
2. Description of related art
In a system equipped with a CPU having the performance of an operating frequency of 100 MHz or more, a cache memory is used in order to cause the CPU to exert its performance to a maximum extent thereby to elevate the performance of the overall system. Of course, in order to maximize the system performance, a maximum operating frequency of the cache memory must follow up the operating frequency of the system. In addition, considering the operation of the overall system, not only the operating frequency of the cache memory but also a holding time of an effective data outputted from the cache memory are important factors.
At present, under the above mentioned circumstances, for the cache memory, a system has been introduced which uses an input control clock mainly for fetching an input signal and an output control clock mainly for controlling the latching of an output signal, for the purpose of elevating the performance of the system.
In the following, an operation of a circuit using two kinds of clocks, namely, an input control clock and an output control clock for the cache memory, will be described.
FIG. 1 is a block diagram illustrating the construction of a prior art cache memory using the input control clock and the output control clock. In FIG. 1, Reference Numeral 51 designates an address register, and Reference Numeral 52 shows a memory cell array. Reference Numeral 53 indicates an output data latch, and Reference Numeral 54 denotes an input data latch. Reference Sign IN0 designates an input signal line to the address register 51, and Reference Sign IN2 shows an output signal line from the address register 51. Reference Sign OUT0 indicates an input signal line to the output data latch 53, and Reference Sign OUT1 denotes an output signal line from the output data latch 53. Reference Sign K1 designates a control clock for fetching the input signal, and Reference Sign K2 shows an output control clock for controlling the latching of an output signal.
FIG. 2 is a block diagram showing the construction of the address register 51. In FIG. 2, IN0 and IN2 are the same as those shown in FIG. 1, and indicate the input signal line to the address register 51 and the output signal line from the address register 51, respectively. Reference Sign IF1 designates a flipflop put into a holding condition in response to a rising of the control clock K1, and Reference Sign IF2 shows a flipflop put into a holding condition in response to a falling of the control clock K1. Reference Sign IN1 indicates a signal line that is both an output signal line of the flipflop IF1 and an input signal line of the flipflop IF2.
The address register 51 is constituted of these two flipflops IF1 and IF2 controlled by the control clock K1. An address is fetched into the memory cell array 52 in response to the control clock K1, and a corresponding address location within the memory cell array 52 is accessed so that an effective data is outputted to the output data latch 53.
Furthermore, the outputted data is fetched in the output data latch 53, and properly outputted and held, i.e., maintained as an output data.
FIG. 3 is a block diagram illustrating the construction of the output data latch 53. Reference Signs OUT0 and OUT1 designate the input signal line to the output data latch 53 and the output signal line from the output data latch 53, respectively, and are the same as those shown in FIG. 1. Reference Sign OF1 shows a flipflop put into a holding condition in response to a falling of the control clock K2. During a period of a high level of the control clock K2, the flipflop OF1 is put in a pass-through condition so that the level on the line OUT0 is transferred to the line OUT1. On the other hand, during a period of a low level of the control clock K2, the level on the line OUT0 is not transferred to the line OUT1, and the level on the line OUT1 is held (for example, the flipflop OF1 holds the value on the line OUT1 at the moment the control clock K2 changes from the high level to the low level).
Now, a fundamental operation of the cache memory shown in FIG. 1 will be described with a signal waveform diagram. FIG. 4 is a waveform diagram when the control clocks K1 and K2 having a desired waveform are supplied. Here, in order to explain the fundamental operation, an example of a read sequence will be described.
First, an address "A1" having an effective period of "tt50" on the signal line IN0 is supplied to the address register 51 in synchronism with the control clock K1. In addition, the address "Al" is transferred to the signal line IN1 in synchronism with the control clock K1, so that finally, the address is transferred to the line IN2 as the input to the memory cell array 52.
Thus, the address "A1" is held as an internal address for a cycle of "tt51".
As a result, an effective data "D1" corresponding to the address "A1" is outputted to the input OUT0 of the output data latch 53 at a time T52. An effective period of this data "D1" is "tt53".
As mentioned above, during the period of the pass-through condition of the output data latch 53, namely, during the high level period (="tt54") of the control clock K2, the effective data "D1" is transferred from the line OUT0, and outputted to the line OUT1 at a time T55.
Thereafter, if the control clock K2 is brought to the low level at a time T56, the output data latch 53 is put into the holding condition, so that the effective data "D1" is held at the line OUT1.
At a time T57, when the control clock K2 is brought to the high level, the output data latch 53 is put in the pass-through condition, so that an indefinite data on the line OUT0 is transferred, and outputted to the line OUT1 at a time T59. In this case, the output data on the line OUT1 has an effective period "tt58".
FIG. 5 is a timing chart for illustrating the operation when the control clock K2 having the high level of the width "tt60" shorter than the desired width "tt54" of the control clock K2 is supplied in the cycle 1. In FIG. 5, the operation until the data is outputted to the line OUT0 is the same as that explained with reference to FIG. 4.
Referring to FIG. 5, the control clock K2 having the high level of the width "tt60" shorter than the desired width is supplied, and the control clock K2 is brought to the low level at a timing T61, so that the output data latch 53 is put into the holding condition. However, since this time T61 is earlier than a time T62 where the effective data "D1" reaches the line OUT0, the effective data "D1" is not held in the output data latch 53, and an indefinite data prior to the effective data "D1" is held in the output data latch 53. In other words, the effective data "D1" is not outputted.
In this case, if the effective period of the output data at the output OUT1 of the output data latch 63 is represented by "tt62", tt62=0. Of course, the memory is defective.
FIG. 6 is a timing chart for illustrating the operation when the control clock K2 having the high level of the width "tt63" longer than the desired width "tt54" of the control clock K2 is supplied in the cycle 1. In FIG. 6, the operation until the data is outputted to the line OUT0 is the same as that explained with reference to FIG. 4.
Referring to FIG. 6, the control clock K2 having the high level of the width "tt63" longer than the desired width is supplied, and the control clock K2 is brought to the low level at a timing T64, so that the output data latch 53 is put into the holding condition. However, since this time T64 is later than a time T65 until which the effective data "D1" is held at the line OUT0, the effective data "D1" is not held in the output data latch 53, and an indefinite data next to the effective data "D1" is held in the output data latch 53. In other words, the effective data "D1" is outputted during only a period of a minimum value "tt66".
In this case, if the effective period of the output data at the output OUT1 of the output data latch 53 is represented by "tt67", comparing "tt67" with the effective period "tt58" of the output data in a normal case, i.e., it becomes tt58&gt;&gt;tt67 ("tt67" is much shorter than "tt58"), with the result that "tt67" is not enough for the CPU in the system to ascertain the effective data. Accordingly, of course, the memory is also defective.
As mentioned above, the prior art semiconductor integrated circuit memory has a problem that, when the falling timing of the control clock for controlling the latching of the output signal varies before and after, in time in particular when the falling timing is advanced, no effective synchronous data can be synchronously latched in the output data latch, and therefore, no effective data can be outputted. Furthermore, there is another problem that, in particular when the falling timing is delayed, the effective data cannot be normally latched in the output data latch, with the result that the indefinite data is latched and on the other hand the effective outputting period of the effective data becomes insufficient for the CPU in the system to recognize the effective data.
Generally, it is difficult to precisely control both the rising timing and the falling timing of the clock in the system. Therefore, it is an ordinary practice that it is attempted to precisely control the rising timing of the clock as being more important to the system. In this case, however, the precision of the falling timing is remarkably deteriorated.
In conclusion, such a situation easily occurs that the falling timing of the control clock for controlling the latching of the output signal varies before and after in time. As a result, such a situation also easily occurs that, as mentioned above the operation of the memory becomes unsatisfactory in the system.